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(R)
TDA7318
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR
INPUT MULTIPLEXER: - 4 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTION TO DIFFERENT SOURCES INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM VOLUME CONTROL IN 1.25dB STEPS TREBLE AND BASS CONTROL FOUR SPEAKER ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIALI2CBUS DESCRIPTION The TDA7318 is a volume, tone (bass and treble) balance (Left/Right) and fader (front/rear) processor for quality audio applications in car radio and Hi-Fi systems. PIN CONNECTION (Top view)
DIP28
SO28
ORDERING NUMBERS: TDA7318 TDA7318D
Selectable input gain is provided. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks andswitches combined with operationalamplifiers. Thanks to the used BIPOLAR/CMOS Tecnology, Low Distortion, Low Noise and Low DC stepping are obtained.
November 1999
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TEST CIRCUIT
THERMAL DATA
Symbol R th j-pins Description Thermal Resistance Junction-pins max SO28 85 DIP28 65 Unit C/W
ABSOLUTE MAXIMUM RATINGS
Symbol VS T amb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.2 -40 to 85 -55 to +150 Unit V C C
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Volume Control 1.25dB step 2db step 1.25dB step -78.75 -14 -38.75 0 100 Bass and Treble Control Input Gain 6.25dB step Parameter Min. 6 2 0.01 106 103 0 +14 0 18.75 0.1 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB dB dB dB
Fader and Balance Control Mute Attenuation 2/14
5.6K C11 2.2F 100nF C14 BOUT(L) TREBLE(L) 4 SPKR ATT 25 MUTE OUT LEFT FRONT 19 18 100nF C15 BIN(L) C17 2.7nF
R2
OUT(L) 17 16
BLOCK DIAGRAM
IN(L)
4x 2.2F C1 L1 RB
15
L1
C2 SPKR ATT 23 MUTE
L2
14
L2 VOL BASS TREBLE
LEFT INPUTS
C3
L3
13
L3
C4
L4
12
L4
OUT LEFT REAR
28 I 2C BUS DECODER + LATCHES 27 26
SCL SDA DIGGND BUS
INPUT SELECTOR + GAIN
C5
R4
8
R4 VOL BASS TREBLE SPKR ATT 24 MUTE OUT RIGHT FRONT
C6
R3
9
R3
RIGHT INPUTS
C7
R2
10
R2
C8
R1
11
R1
4x 2.2F RB
SPKR ATT 22 MUTE 1 CREF C9 C10 2.2F 22F OUT(R) IN(R) 7 6 21 BOUT(R) 100nF C12 5.6K R1 20 BIN(R) 100nF C13 2.7nF C16 5 TREBLE(R)
D95AU265
SUPPLY
OUT RIGHT REAR
2
3
VCC
AGND
TDA7318
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ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all controls flat (G = 0), f = 1KHz unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection 6 4 60 9 8 85 10 11 V mA dB
INPUT SELECTORS
R II V CL SIN RL GINmin GINmax GSTEP eIN VDC Input Resistance Clipping Level Input Separation (2) Output Load resistance Min. Input Gain Max. Input Gain Step Resolution Input Noise DC Steps G = 18.75dB adjacent gain steps G = 18.75 to Mute pin 7, 17 Input 1, 2, 3, 4 35 2 80 2 -1 17 5 0 18.75 6.25 2 4 4 20 1 20 7.5 50 2.5 100 70 K Vrms dB K dB dB dB V mV mV
VOLUME CONTROL
R IV C RANGE AVMIN AVMAX ASTEP EA ET VDC Input Resistance Control Range Min. Attenuation Max. Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps adjacent attenuation steps From 0dB to Av max 0 0.5 Av = 0 to -20dB Av = -20 to -60dB 20 70 -1 70 0.5 -1.25 -3 33 75 0 75 1.25 0 50 80 1 80 1.75 1.25 2 2 3 7.5 k dB dB dB dB dB dB dB mV mV
SPEAKER ATTENUATORS
Crange SSTEP EA AMUTE VDC Control Range Step Resolution Attenuation set error Output Mute Attenuation DC Steps adjacent att. steps from 0 to mute 80 100 0 1 3 10 35 0.5 37.5 1.25 40 1.75 1.5 dB dB dB dB mV mV
BASS CONTROL (1)
Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +12 1 34 +14 2 44 +16 3 58 dB dB K
TREBLE CONTROL (1)
Gt TSTEP Control Range Step Resolution Max. Boost/cut +13 1 +14 2 +15 3 dB dB
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TDA7318
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUTS
VOCL RL CL ROUT VOUT Clipping Level Output Load Resistance Output Load Capacitance Output resistance DC Voltage Level 30 4.2 75 4.5 d = 0.3% 2 2 10 120 4.8 2.5 Vrms K nF V
GENERAL
e NO Output Noise BW = 20-20KHz, flat output muted all gains = 0dB A curve all gains = 0dB S/N d Signal to Noise Ratio Distortion all gains = 0dB; VO = 1Vrms AV = 0, VIN = 1Vrms AV = -20dB VIN = 1Vrms V IN = 0.3Vrms 80 AV = 0 to -20dB -20 to -60 dB 2.5 5 3 106 0.01 0.09 0.04 103 0 0 1 2 0.1 0.3 V V V dB % % % dB dB dB
15
Sc
Channel Separation left/right Total Tracking error
BUS INPUTS
V IL VIH IIN VO
Notes: (1) Bass and Treble response see attached diagram (fig.19). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network (2) The selected input is grounded thru the 2.2F capacitor.
Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5
1 +5 0.4
V V A V
Figure 1: Noise vs. Volume/Gain Settings
Figure 2: Signal to Noise Ratio vs. Volume Setting
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Figure 3: Distortion & Noise vs. Frequency Figure 4: Distortion & Noise vs. Frequency
Figure 5: Distortion vs. Load Resistance
Figure 6: Channel Separation (L R) vs. Frequency
Figure 7: Input Separation (L1 L2, L3, L4) vs. Frequency
Figure 8: Supply Voltage Rejection vs. Frequency
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Figure 9: Output Clipping Level vs. Supply Voltage Figure 10: Quiescent Current vs. Supply Voltage
Figure 11: Supply Current vs. Temperature
Figure 12: Bass Resistance vs. Temperature
Figure 13: Typical Tone Response (with the ext. components indicated in the test circuit)
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TDA7318
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7318 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 14, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.15 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 14: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 16). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Figure 15: Timing Diagram of I2CBUS
Figure 16: Acknowledge on the I2CBUS
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SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7318 address (the 8th bit of the byte must be 0). The TDA7318 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
TDA7318 ADDRESS MSB S 1 0 first byte 0 0 1 0 0 LSB 0 ACK MSB DATA LSB
ACK
MSB DATA
LSB
ACK P
Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION Chip address
1 MSB 0 0 0 1 0 0 0 LSB
DATA BYTES MSB 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 B2 0 1 0 1 0 1 1 B1 B1 B1 B1 B1 G1 0 1 B0 B0 B0 B0 B0 G0 C3 C3 A2 A2 A2 A2 A2 S2 C2 C2 A1 A1 A1 A1 A1 S1 C1 C1 LSB A0 A0 A0 A0 A0 S0 C0 C0 FUNCTION Volume control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 6.25dB steps
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SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) Volume
MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 FUNCTION Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70
For example a volume of -45dB is given by: 00100100
Speaker Attenuators
MSB 1 1 1 1 0 0 1 1 0 1 0 1 B1 B1 B1 B1 B0 B0 B0 B0 A2 A2 A2 A2 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 A1 A1 A1 A1 0 0 1 1 0 0 1 1 LSB A0 A0 A0 A0 0 1 0 1 0 1 0 1 FUNCTION Speaker LF Speaker RF Speaker LR Speaker RR 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 Mute
For example attenuation of 25dB on speaker RF is given by: 10110100
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Audio Switch
MSB 0 1 0 G1 G0 S2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 S1 0 0 1 1 0 0 1 1 LSB S0 0 1 0 1 0 1 0 1 FUNCTION Audio Switch Stereo 1 Stereo 2 Stereo 3 Stereo 4 Not allowed Not allowed Not allowed Not allowed +18.75dB +12.5dB +6.25dB 0dB
For example to select the stereo 2 input with a gain of +12.5dB the 8bit string is: 01001001
Bass and Treble
0 0 1 1 1 1 0 1 C3 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Bass Treble -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14
C3 = Sign For example Bass at -10dB is obtained by the following 8 bit string: 01100010
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TDA7318
mm MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
DIM.
OUTLINE AND MECHANICAL DATA
SO28
8 (max.)
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DIM. MIN. a1 b b1 b2 D E e e3 F I L 15.2 0.23
mm TYP. 0.63 0.45 0.31 1.27 37.34 16.68 2.54 33.02 14.1 4.445 3.3 0.598 0.009 MAX. MIN.
inch TYP. 0.025 0.018 0.012 0.050 1.470 0.657 0.100 1.300 0.555 0.175 MAX.
OUTLINE AND MECHANICAL DATA
DIP28
0.130
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved 2 2 2 Purchase of I C Components of STMicrolectronics, conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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